module top (
    input input_clk,
    input rst_n,

    input  miso,
    output cs,
    output sck,
    output mosi,

    output [7:0] out
);

  wire sys_clk;  //synthesis keep;
  wire uart_clk;
  wire clk_5m;
  wire clk_20m;
  wire extlock;

  //		Clock name	| Frequency 	| Phase shift
  //		C0        	| 100.000000MHZ	| 0  DEG     
  //		C1        	| 200.000000MHZ	| 0  DEG     
  //		C2        	| 5.000000  MHZ	| 0  DEG     
  //		C3        	| 20.000000 MHZ	| 0  DEG 
  PLL u_pll (
      .refclk  (input_clk),
      .reset   (~rst_n),
      .extlock (sys_rst_n),
      .clk0_out(O_clk0),
      .clk1_out(O_clk1),
      .clk2_out(O_clk2),
      .clk3_out(O_clk3)
  );
  assign sys_clk  = O_clk0;
  assign uart_clk = O_clk1;
  assign clk_5m   = O_clk2;
  assign clk_20m  = O_clk3;

  spi_send_n spi_send_n_inst (
      .sys_clk(sys_clk),
      .sys_rst_n(sys_rst_n),
      .miso(),
      .cs(cs),
      .sck(sck),
      .mosi(mosi)
  );

  assign out[0] = mosi;
  assign out[1] = miso;
  assign out[2] = sck;
  assign out[3] = cs;

endmodule

